Semester project for 36APC course
Mastermind game


Implement Mastermind game on Spartan IIe FPGA mounted on Digilab DIO1 I/O board. Game is being played in following steps.

Game is finished when the second player correctly guessed colour for all 4 positions that means he scores 4 black marks.


Basic game scenario transformed to the Digilab board design is following:

Scoring is done automatically after colours’ input phase: first two digits show number of guesses, third is number of white marks, fourth number of black marks. To continue with colours select one needs to press BTN5 again.  When second player scores 4 black marks, game ends. A new one can be started pressing button BTN1 (reset).

We have decided to implement the game using VHDL language and Xilinx ISE development environment in its 5.2 version. Basic overview of realised blocks on RTL level is shown on the following picture.

Fig. 1

Overview of buses, signals and their types:

The final realisation is best described with ISE files. They are part of the solution, packaged in ZIP archive:


The Mastermind game was designed and implemented without larger difficulties. Problem analysis and structure design took 1 hour of project time; the realisation took 11 hours and the documentation phase 1 hour. While implementing the project we have encountered synthesis problems in final stages, problems with clock setup and with time constrains during communication. All problems were solved.